The present invention relates to a semiconductor device, and particularly to an MOS semiconductor device with high withstand voltage, and a method of manufacturing the same.
FIG. 3 is a sectional view showing a conventional manufacturing step sequence of an MOS semiconductor device. FIG. 3(a) shows a state in which after a gate electrode 104 is formed on a gate insulating film 103 on a semiconductor substrate 101, the gate insulating film 103 on such portions as to be formed into a source diffusion and a drain diffusion 102, 102, and under the end of the gate electrode 104 is wet etched. In order to assure the reliability of a semiconductor device, it is normally necessary to set the thickness of the gate insulating film 103 made of a silicon thermal oxidation film to about 3 MV/cm. For example, in a high withstand voltage MOS semiconductor device, when 30 V is applied between the gate electrode 104 and the semiconductor substrate 101, the oxide film thickness of 1000 .ANG. is required. In that case, when impurities are implanted by using a high current ion implantation apparatus at the subsequent formation of a source and drain, it is difficult to sufficiently implant the impurities into the semiconductor substrate due to the restriction of an implantation energy. Thus, it is necessary to etch the gate insulating film on such portions as to be formed subsequently into the source diffusion and drain diffusion by wet etching after the gate electrode is formed. However, since the wet etching is isotropic, the gate insulating film 103 under the end of the gate electrode 104 is also etched.
Next, as shown in FIG. 3(b), an oxide film 105 is formed on the semiconductor substrate 101 and the surface of the gate electrode 104 by a thermal oxidation method, and impurity implantation is carried out by using the high current ion implantation apparatus to form the source diffusion 102 and the drain diffusion 102. When the thickness of the oxide film is made about 200 .ANG. at this time, the impurity implantation is sufficiently carried out. Thereafter, as shown in FIG. 3(c), an intermediate insulating film 107 is formed by a CVD method.
In the MOS semiconductor device manufactured by the above conventional manufacturing method, spaces 108 are formed at overlap portions between the gate electrode 104 and the source diffusion 102/drain diffusion 102, and the spaces 108 cause the reliability of the MOS semiconductor device to be extremely lowered.